1. Field of the Invention
The present invention relates to a method of forming an electrically programmable read-only memory, and more specifically, to an electrically programmable read-only memory with a low leakage current.
2. Description of Background
Electronic memory comes in a variety of forms to serve a variety of purposes. A non-volatile memory is used for easy and fast information storage in such devices as personal digital assistants (PDA), digital cameras,cellular phones, and home video game consoles. It is often desirable to combine many functions on a single device, also called a system-on-a-chip (SOC), to reduce the number and cost of chips. Embedding flash memory allows a single chip produced by a manufacturer to be configured for a variety of applications, and/or allows a single device to be configured by a user for different applications.
A non-volatile memory consists of a plurality of identical non-volatile memory cells. For simplicity, a single non-volatile memory cell is illustrated. Please refer to FIG. 1, which shows a cross-sectional view of a conventional non-volatile memory cell 10. The non-volatile memory cell 10 includes a first PMOS transistor 12 and a second PMOS transistor 14, both transistors formed on an N-well 16, the second PMOS transistor 14 and the first PMOS transistor 12 having a second p+ doped region 20 in common. The first PMOS transistor 12 includes a drain (i.e. a first p+ doped region 18), a control gate 24 formed between the first p+ doped region 18 and the second p+ doped region 20, a source (i.e. the second p+ doped region 20), and an oxide layer 34 formed between the control gate 24 and the N-well 16. The second PMOS transistor 14 includes a drain (i.e. the second p+ doped region 20), a source (i.e. a third p+ doped region 22), a floating gate 26 that is an n-type single-polysilicon, and an oxide layer 32 formed between the floating gate 26 and the N-well 16.
Please refer to FIG. 2A and FIG. 2B. FIG. 2A is a band diagram of the conventional non-volatile memory cell 10 before erasing data with ultraviolet (UV) light, and FIG. 2B is a band diagram of the conventional non-volatile memory cell 10 after erasing data with ultraviolet (UV) light, where Ec represents a conduction band, Ev represents a valence band, Ef represents Fermi level, and arrow 1 represents a direction associated with an electric field. As shown in FIG. 2A, during equilibrium, a vacuum level of a semiconductor must be under a continuous state, and the Fermi level must be under the identical level. While intending to erase data within the non-volatile memory cell 10, the entire non-volatile memory cell 10 is exposed to the UV light. Theoretically, the free electrons initially stored within the floating gate 26 excited by the UV light will pass through oxide layer 32. However, as it is, due to E=xe2x88x92(dV/dx) with E being the electric field, V the electric potential, and x the direction, that is, the electric field is a negative gradient of electric potential. When electrons initially stored within the floating gate 26 leave, an electric field (arrow 1), resulting from an electric potential Vbi, induces the electrons within the N-well 16 passing through the oxide layer 32 and flowing into the floating gate 26 more easily, generating a leakage current. The induced leakage current and the static power dissipation are thus increased. Besides, the residual electrons and ions can further diffuse into the source 22 or drain 20 and accumulate on the interface between the source 22 or drain 20 and the N-well 16 so as to result in a decreased junction breakdown voltage, leading to the malfunction of the device.
Accordingly, the purpose of the claimed invention is providing an electrically programmable read-only memory(EPROM) having a new structure of a non-volatile memory cell for reducing a leakage current of a metal-oxide semiconductor(MOS) transistor to solve above-mentioned problem.
The method of the claimed invention includes forming a first p+ doped region, a second p+ doped region, and a third p+ doped region on an N-well, forming a control gate between the first p+ doped region and the second p+ doped region, and forming a p-type floating gate between the second p+ doped region and the third p+ doped region.
The method of the claimed invention also includes forming a first p+ doped region, a second p+ doped region and a third p+ doped region on an N-well, forming a control gate between the first p+ doped region and the second p+ doped region, forming an n-type floating gate between the second p+ doped region and the third p+ doped region, and increasing donor ions implanted within the N-well between the second p+ doped region and the third p+ doped region.